1. Field of the Invention
The present invention relates to a stack package and method for fabricating the same, particularly the stack package is characterized in that one package consists at least two semiconductor chips stacked therein.
2. Description of the Related Art
Rapid progress in the memory chip has been presented to increase memory capacity. Currently, 128M DRAM is mass-produced, and also the mass-production of 256M DRAM will be available sooner or later.
For increasing memory chip capacity, i.e. high integration, a technology for inserting cells as many as possible into a given area of semiconductor device, is widely known. However, this method requires high technology such as a precise line width and a considerable amount of time for development. Accordingly, a relatively simpler stacking technology to optimize integrity of the semiconductor device has been developed most recently.
The term stacking used in semiconductor industry means a technique to double the memory capacity by heaping up at least two semiconductor chips in a vertical direction. According to the stacking technique, a 128M DRAM device can be constituted by two 64M DRAM devices for instance, also a 256M DRAM device can be constituted by two 128M DRAM devices.
There are various applications of the stacking such as, stacking for semiconductor devices, stacking for packages or modules. Stacking for packages means that pre-formed packages are stacked in several layers or more. This stacking is regarded as a cost-effective method. There are two types of package stacking technology. For instance, packages ready-made upon order are used and each lead of the packages is connected to its corresponding lead. The other stacking technology uses standard packages which are connected by side rails or accessories similar to the side rails.
Hereinafter, a brief description regarding the above-mentioned typical stacking technology for packages is given with reference to FIGS. 1 and 2.
As shown in the drawings, a bottom surface of an upper package 1 is faced with a top surface of a lower package 1'. In the respective packages, leads 1a,1b being projected from both sides of the packages are electrically connected. Although only two packages are shown in the drawings, however more packages can be stacked. Furthermore, leads of the stack packages are connected by side rails or auxiliary accessories similar to the side rails.
However, the package as described above incurs following problems. Since two or more packages are stacked, the size of package is increased and therefore it is very difficult to handle with the package. A number of steps, mostly in molding step and forming step are also added or transformed. Particularly, it is possible to stack only provided that the leads are transformed, even when the step for forming is already performed, and sometimes it is impossible to stack due to the work condition which depends on width or space of the leads.
On the other hand, to solve the foregoing problems a stack package comprising at least two semiconductor chips in a package is disclosed in Japanese Patent Laid-open No. 62-8529, No. 62-131555 and No. 63-124450. Those references, however have following problems respectively.
The Japanese Patent Laid-open No. 62-8529 and No. 62-131555 disclose a stack package having semiconductor chips mounted on both sides of a tape automated bonding (hereinafter referred as to TAB) tape. In that structure, a wire bonding step is preferentially performed, i.e. a bonding pad disposed on one side of the semiconductor chip is connected to a lead frame by means of a metal wire. Afterward, a subsequent wire bonding step follows, i.e. another bonding pad disposed on the other side of the semiconductor chip is connected to another lead frame by means of a metal wire. While the subsequent wire bonding steps are performed, the metal wire which is already connected during the precedent wire bonding step, is often damaged.
Also, the Japanese Patent Laid-open No. 63-124450 discloses a stack package that a two-layered lead frame is molded with an epoxy compound. However, it is difficult to mass-produce the stack package as constituted above according to the currently used transfer molding technique.
In addition, the Japanese Patent Laid-open No. 63-119952 discloses a stack package having a structure that its lead frames are connected each other. However, in the stack package, it is difficult to form a lead frame for connecting lead frames which are already made before molding the structure. Moreover, this structure expands package size opposite to the high integration trend in the package industry.